library verilog;
use verilog.vl_types.all;
entity Permuted_Choice_1 is
    port(
        Permuted_Choice_1_Input: in     vl_logic_vector(64 downto 1);
        Permuted_Choice_1_Select: in     vl_logic;
        Left            : out    vl_logic_vector(28 downto 1);
        Right           : out    vl_logic_vector(28 downto 1);
        Permuted_Choice_1_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end Permuted_Choice_1;
